An embodiment of the present invention relates to a technology field for a liquid crystal display, and to a shift register and a gate line driving device thereof.
A pixel array of a liquid crystal display includes a multiple rows of gate lines and a multiple columns of data lines which are interlaced. Wherein, a gate line driving device consisted of a plurality of shift registers provides a switch signal for the multiple rows of gate lines of pixel array, thereby controlling the multiple rows of gate lines being switched on in order, and the pixel electrodes in the pixel array are charged by the corresponding row of data lines, in order to form a gray voltage required for displaying each gray scale of an image, and then display each frame of image.
As shown in FIG. 1, the existing gate line driving device includes a plurality of shift registers, wherein a output OUTN of the Nth stage of shift register is not only fed back to the (N−1)th stage of shift register to switch off the (N−1)th stage of shift register, but also outputted to the (N+1)th stage of shift register as a trigger signal for the (N+1)th stage of shift register. While as shown in FIG. 2, when a output of one stage of shift register is used as the trigger signal of another stage of shift register, since the load connected with the output terminal is large, a signal approximating a square wave at the input terminal will be delayed at the output terminal, a phenomenon of two sequential rows of gate lines being concurrently switched on will happen when the delay is large, also the pixel array will generate interference with the output terminal, thereby making the stability for the signal of the output terminal insufficient, which all easily generate a read/write error, therefore affecting the quality of the image.
Moreover, when the output of one stage of shift register is used as the trigger signal of another stage of shift register, clock signals CLK, CLKB need be triggered synchronously with the output, as shown in FIG. 3, so a duty ratio for the clock signals CLK, CLKB need to be maintained as 50%, which makes no reserved spare time between the driving of the two rows of gate line, thus it can not ensure that another stage of shift register will not be switched on until one stage of the shift register has been switched off sufficiently, therefore it will also cause two continuous rows of gate lines being concurrently switched on, thus making the signal crosstalk happened, eventually affecting the quality of the image.